Estimating BIST Resources in High-level Synthesis

Estimation of resources at various stages of the high-level synthesis process is essential to guide high-level synthesis algorithms towards optimal solutions. Lower bound es timation bounds the design space and gives an indication of the quality of the design synthesized. Previous work in high-level synthesis focused on bounds on functional resources. In this paper, we present lower bounds on the number of test resources (i.e. test pattern generators, signature analyzers and CBILBO registers) required to test the synthesized data path by the partial intrusion built-in self-test (BIST) method ology. The estimation is performed on scheduled data flow graphs and provides a practical way of selecting or modifying module assignments and schedules such that the synthesized data path requires a small number of test resources to test it. "This work was supported by the Advanced Research Projects Agency and monitored by the Department of the Army, Ft.Huachuca, under Contract No. DABT63-95-C-0042. The information reported here does not necessarily reflect the position or the policy of the Government and no official endorsement should be inferred.